1. Field of the Disclosure
The present disclosure relates generally to a semiconductor memory device. More particularly, the invention relates to a semiconductor memory device capable of reducing current consumed when a sensing operation is performed and thus can reduce power consumption.
2. Description of Related Art
In order to select a single cell from a DRAM and to read data from the cell, a word line and a bit line pair are typically selected. Because the voltage differential in reading the data of the selected cell is low, however, the selected cell is usually sensed. Typically, all the cells coupled to a single word line are sensed due to refresh. Sensing a cell usually involves applying the potential of the power supply voltage to a restore node of a sense amplifier and applying the potential of the ground voltage to a sensing bar node. Due to this, a large amount of current is typically required to sense the cells of a word line, and much power is consumed. Additionally, this may cause variations in the power supply voltage, leading to errors. Further, it is expected that the power consumption in a low power market using a battery will be an important problem.
After the sensing operation is performed, the word line, the restore node, the sensing bar node, and the bit line pair that were activated during the sensing operation are precharged to a bit line precharge voltage level before a next word line is activated. This may cause electric charges stored at the capacitor, which is charged with a HIGH or LOW level, to be unnecessarily discharged.
Some embodiments of the present invention may solve one or more (or none) of the above problems. Some embodiments of the present invention provide a semiconductor memory device capable of reducing current consumed when a sensing operation is performed and thus reduce power consumption.
In one embodiment, a semiconductor memory device is provided in which a potential of a restore node and a sensing bar node is raised to a given potential before a sensing operation is performed. After the sensing operation is performed, discharged electric charges may be stored and then used in a next sensing operation. Thus, the power consumption of the semiconductor memory device may be reduced.
In one specific embodiment, a semiconductor memory device is provided. The memory device includes a memory cell array comprising a plurality of cells, and a plurality of sense amplifiers coupled to respective bit lines and respective bit-bar lines of respective cells in the plurality of cells, each of the plurality of sense amplifiers having a first terminal and a second terminal. The memory device also includes a control signal generating circuit, driven by a plurality of signals for sensing the cells of the memory cell array, to generate first-third control signals. The memory device additionally includes first switching means, driven by the first control signal, for supplying the first terminals of the plurality of sense amplifiers with a power supply voltage, and second switching means, driven by the second control signal, for supplying the second terminals of the plurality of sense amplifiers with a ground voltage. The memory device further includes a charge recycling circuit, driven by a power-up signal and the third control signal, to supply the first terminals of the plurality of sense amplifiers with electric charges of a first given potential and to supply the second terminals of the plurality of sense amplifiers with electric charges of a second given potential, or to store the electric charges of the first terminals and to store electric charges of the second terminals, depending on operation of the plurality of sense amplifiers.